A double data rate (DDR) synchronous dynamic random access memory (SDRAM) was introduced as a new evolutionary dynamic random access memory (DRAM) to provide a high-performance interface for system memory. As the DDR data rate increases, high-frequency phenomena, such as, channel resonance, inter-symbol interference (ISI), cross-talk, and simultaneous switching noise (SSN), have become critical in determining the performance of memory.
In a typical computer system, memory devices (e.g., SDRAM) are mounted on one or more dual in-line memory module (DIMM). The DIMM is then plugged into a motherboard via a DIMM connector to provide an interface between the memory and the motherboard.
FIG. 1 shows an existing DIMM. The interface includes a number of transmission lines 130, also known as traces, coupling a DIMM connector 110 to a number of SDRAM devices 120. In addition to the transmission lines 130, a resistor 140 is coupled in series with the transmission lines 130 to provide a signal path from the DIMM connector 110 to the SDRAM devices 120. The connector 110, the transmission lines 130, and the resistor 140 may be fabricated on a printed circuit board. The existing DIMM has a relatively low slew rate and low voltage swing margin at a high frequency, such as, 300 MHz, because the SDRAM device parasitic, such as parasitic inductance and parasitic capacitance, limits the signal gain of the interface. As a result, the signal quality is worsened.
Furthermore, to predict the performance in high-frequency phenomena, and consequently, to improve the memory channel, series of time domain analysis and simulations are performed to design a memory interface. As the memory interface becomes more and more complex, the large amount of time-domain simulation takes a long time to complete. To compete efficiently in the market, the design time of memory interface has to be shortened in order to provide customers with the memory interface sooner.